1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, more particularly relates to a method for manufacturing a CMOS semiconductor device which sufficiently activates an impurity introduced into a polycrystalline silicon gate electrode and reduces an effective thickness of the gate insulating film.
2. Description of the Related Art
The increasing miniaturization of CMOS transistors has led to demand for a shallower junction between the source region and drain region. To obtain such a shallower junction, it is required that ions be implanted with a low energy and the activation annealing be performed at a lower temperature and in a shorter time than the past. When using polycrystalline silicon as a gate electrode, if annealing at a low temperature for a short time, the impurity implanted into the polycrystalline silicon gate electrode is not sufficiently activated. Therefore, the gate electrode becomes depleted and the effective thickness of the gate insulating film becomes greater resulting in the problem of the performance of the CMOS transistor dropping. To solve this problem, Japanese Unexamined Patent Publication (Kokai) No. 6-310666 (in particular the claims and paragraph) discloses a method of manufacturing a CMOS transistor using predoping for introducing an impurity into a gate electrode formation material in advance before processing to the shape of the gate electrode. This publication describes to form a polycrystalline silicon film on a gate oxide film, implant boron (B) ions into the region of the polycrystalline silicon film for forming the p-type gate electrode (pMOS formation region), implant phosphorus (P) ions into the region of the polycrystalline silicon film for forming the n-type gate electrode (nMOS formation region), perform activation annealing at these regions simultaneously, then process them to form gate electrode shapes. The activation annealing is performed specifically at about 850° C. for 30 minutes in a nitrogen atmosphere. However, when annealing for such a long time, the predoped boron migrates from the gate electrode through the gate oxide film to the substrate side. The so-called “boron penetration” phenomenon occurs. This boron penetration ends up causing the performance of the transistor to drop. In this way, while it is desirable to apply sufficient heat for annealing in order to activate the predoped material, if too much heat is added, boron penetration ends up occurring. Improvement of the activation and boron penetration are in a trade-off relationship resulting in a narrow margin of processing and difficult production.
Further, the gate width of the gate electrode has to be made narrower to miniaturize a CMOS transistor. If the gate width becomes narrower, the resultant roughness of the gate shape will lead to variations in the transistor characteristics. Further, it is known that with predoping, the roughness of the gate shape also becomes larger. This increase in roughness is particularly remarkable at the n-type gate electrode side (for example, see Sugatani, S. et al., “Requirements for Dry Process of 100 nm Node CMOS Integration”, Dry Process International Symp. 2002, pp. 255-262).